TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 30

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

(3) IDLE0, SLEEP0 mode (IDLE0, SLEEP0)
(Normal release mode)
and the time base timer control register (TBTCR). The following status is maintained
during IDLE0 and SLEEP0 modes.
Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) periperals.
a.
b.
c.
IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2)
Timing generator stops feeding clock to peripherals except TBT.
The data memory, CPU registers, program status word and port output latches
are all held in the status in effect before IDLE0 and SLEEP0 modes were entered.
IDLE0 and SLEEP0 modes.
The program counter holds the address 2 ahead of the instruction which starts
Figure 1.4.14 IDLE0, SLEEP0 Mode
No
“0”
No
“0”
“1”
the IDLE0, SLEEP0 mode
Starting IDLE0, SLEEP0
instruction which follows
CPU, WDT are halted
Stopping Peripherals
Interrupt processing
mode by instruction
EEPCR<ATPWDW>
TBTCR<TBTEN>
Execution of the
start instruction
86FM48-26
by instruction
TBT interrupt
source clock
Reset input
falling edge
CPU wait
enable
TBT
IMF
Yes
No
Yes
“0”
“1”
“1” (Interrupt release mode)
Yes
Note 1: EEPCR<ATPWDW>
Note 2: During
Reset
EEPCR, which is a control bit of the
power supply circuit for Flash.
operations remain halted, but the
peripheral
resumed. Therefore in this time, though
the interrupt latch might be set,
interrupt operation is not executed until
the CPU wait is finished.
CPU
function
wait,
is
though
operation
a
TMP86FM48
2007-08-24
bit1
CPU
in
is