TMP86xy48UG/FG Toshiba, TMP86xy48UG/FG Datasheet - Page 166

• Manufacturer Part Number: TMP86xy48UG/FG
• Manufacturer: Toshiba

Specifications of TMP86xy48UG/FG

• Package: LQFP64/QFP64
• Rom Types (m=mask,p=otp,f=flash): F/E
• Rom Size: 32
• Ram Size: 2K
• Driver Led: 11
• Driver Lcd: -
• Spi/sio Channels: 1
• Uart/sio Channels: 1
• I2c/sio Channels: 1
• High-speed Serial Output: 2
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 2
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 54
• Power Supply (v): 2.7 to 3.6

Program execution area
EEPCR<MNPWDW>
FLASH warm-up counter
FLASH control circuit status
Operation mode
EEPCR<ATPWDW>
EEPSR<EWUPEN>
EEPSR<BFBUSY>
Figure 2.17.7 Automatic Power Control for the FLASH Control Circuit (EEPCR<ATPWDW>)
2.17.5.2 Automatic Power Control for the FLASH Control Circuit (EEPCR<ATPWDW>)
Note 1: The EEPCR<ATPWDW> functions only if the EEPCR<MNPWDW> is “1”. If the
Note 2: During an FLASH warm-up (CPU wait), the peripheral circuits continue operating,
circuit. It is possible to suppress power consumption by automatically shutting down
the power for the FLASH control circuit when an operation mode is changed to
IDLE0/1/2 and SLEEP0/1/2 modes. This bit can be specified regardless of the area in
which a program is being executed.
(IDLE0/1/2 or SLEEP0/1/2) where the CPU is at a halt automatically turns off the
power for the FLASH control circuit. Once the operation mode is released, the
warm-up time (CPU wait) is automatically counted to resume normal processing. The
CPU wait period is either 2
EEPCR<ATPWDW> is “1”, releasing the operation mode does not cause the CPU wait.
for the FLASH control circuit regardless of the setting of the EEPCR<ATPWDW>.
When the STOP mode is released, a STOP mode oscillation warm-up is carried out,
and then an FLASH control circuit warm-up (CPU wait) is automatically performed. If
the EEPCR<MNPWDW> is “0”, entering/exiting a STOP mode allows the power for
the FLASH control circuit to be kept turned off.
The EEPCR<ATPWDW> is an automatic power control bit for the FLASH control
After the EEPCR<ATPWDW> is cleared to “0”, entering an operation mode
If EEPCR<MNPWDW> = “1”, executing a STOP mode forcibly turns off the power
EEPCR<MNPWDW> is “0”, the power for the FLASH control circuit is kept turned
off when an operation mode is executed or released.
but the CPU stays at a halt. Even if an interrupt latch is set under this condition, no
interrupt process occurs until the CPU wait is completed. If the IMF is “1” when the
interrupt latch is set, interrupt process takes place according to the interrupt priority
after the CPU has started operating.
NORMAL or SLOW mode
Normal operation
Specify ATPWDW = 0
0
86FM48-162
IDLE or SLEEP mode
10
Power-off state
/fc (SYSCK = “0”) or 2
FLASH area or RAM area
Warm-up in progress
2
10
/fc or 2
CPU WAIT
Overflow
3
/fs [s]
3
/fs (SYSCK = “1”). If the
NORMAL or SLOW mode
Normal operation
TMP86FM48
2007-08-24
0