st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 116

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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The OCF1 bit cannot be set by hardware in one pulse mode but the OCF2 bit can generate
an output compare interrupt.
When the pulse width modulation (PWM) and one pulse mode (OPM) bits are both set, the
PWM mode is the only active one.
If OLVL1 = OLVL2 a continuous signal is seen on the OCMP1 pin.
The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to
perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take
care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can
also generates interrupt if ICIE is set.
When one pulse mode is used OC1R is dedicated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time has been elapsed but cannot generate an
output waveform because the level OLVL2 is dedicated to the one pulse mode.
Figure 51. One pulse mode timing example
1. IEDG1 = 1, OC1R = 2ED0h, OLVL1 = 0, OLVL2 = 1
Figure 52. Pulse width modulation mode timing example
1. OC1R = 2ED0h, OC2R = 34E2, OLVL1 = 0, OLVL2 = 1
Pulse width modulation mode
Pulse width modulation (PWM) mode enables the generation of a signal with a frequency
and pulse length determined by the value of the OC1R and OC2R registers.
Pulse width modulation mode uses the complete output compare 1 function plus the OC2R
register, and so this functionality can not be used when PWM mode is activated.
In PWM mode, double buffering is implemented on the output compare registers. Any new
values written in the OC1R and OC2R registers are loaded in their respective shadow
registers (double buffer) only at the end of the PWM period (OC2) to avoid spikes on the
PWM output pin (OCMP1). The shadow registers contain the reference values for
comparison in PWM ‘double buffering’ mode.
Counter 34E2
OCMP1
Counter
OCMP1
ICAP1
IC1R
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
01F8
Compare2
FFFC FFFD FFFE
FFFC FFFD FFFE
OLVL2
OLVL2
01F8
2ED0 2ED1 2ED2
2ED0 2ED1 2ED2
Compare1
Compare1
OLVL1
OLVL1
2ED3
FFFC FFFD
2ED3
Compare2
34E2 FFFC
OLVL2
OLVL2