st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 39

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
5.3.4
Condition code register (CC)
The 8-bit condition code register contains the interrupt masks and four flags representative
of the result of the instruction just executed. This register can also be handled by the push
and pop instructions.
These bits can be individually tested and/or controlled by specific instructions.
Table 5.
CC
5, 3
Bit
4
2
7
(half carry)
(negative)
(interrupt)
Name
R/W
I1, I0
1
H
N
CC register description
6
Interrupt management bits
Arithmetic management bit
Arithmetic management bit
The combination of the I1 and I0 bits gives the current interrupt software
priority:
10: Interrupt software priority = level 0 (main)
01: Interrupt software priority = level 1
00: Interrupt software priority = level 2
11: Interrupt software priority = level 3 (interrupt disable)
These two bits are set/cleared by hardware when entering in interrupt. The
loaded value is given by the corresponding bits in the interrupt software
priority registers (IxSPR). They can be also set/cleared by software with the
RIM, SIM, IRET, HALT, WFI and push/pop instructions. See
Interrupts on page 59
This bit is set by hardware when a carry occurs between bits 3 and 4 of the
ALU during an ADD or ADC instructions. It is reset by hardware during the
same instructions.
0: No half carry has occurred
1: A half carry has occurred
This bit is tested using the JRH or JRNH instruction. The H bit is useful in
BCD arithmetic subroutines.
This bit is set and cleared by hardware. It is representative of the result sign
of the last arithmetic, logical or data manipulation. It’s a copy of the result 7th
bit.
0: The result of the last operation is positive or null
1: The result of the last operation is negative (that is, the most significant bit
This bit is accessed by the JRMI and JRPL instructions.
is a logic 1)
R/W
I1
5
R/W
H
4
for more details.
R/W
I0
3
Function
R/W
N
2
Central processing unit
Reset value: 111x 1xxx
R/W
1
Z
Section 7:
R/W
C
0
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