st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 218

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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Figure 94. C
1. Register updated on R event.
An overflow of the MTIM timer generates an RPI interrupt if the RIM bit is set.
When simulated commutation mode is enabled, the D and Z events are not ignored by the
peripheral; this means that if a Z event happens, the MTIM 8-bit internal counter is reset.
To generate consecutive simulated commutations (C
written in the MCOMP register only after a C event generation. Otherwise, the C event never
occurs.
When simulated commutation mode is enabled, the built-in check is active, so if the value
written in the MCOMP register is less than or equal to MTIM, the C event is generated and
the data in the MCOMP register are overwritten by the MTIM value.
Auto-updated step ratio register
In switched mode: the MTIM timer is driven by software only and any prescaler change
has to be done by software (see
In autoswitched mode: an auto-updated prescaler always configures the MTIM timer for
best accuracy.
–
–
When the MTIM timer value reaches 100h, the prescaler is automatically
incremented in order to slow down the MTIM timer and avoid an overflow. To keep
consistent values, the MTIM register and all the relevant registers are shifted right
(divided by two). The RPI bit in the MISR register is set and an interrupt is
generated (if RIM is set). The timer restarts counting from its median value 0 x 80h
and if the TES[1:0] bits = 00, the OI bit in the MCRC register is set.
When a Z-event occurs, if the MTIM timer value is below 55h, the prescaler is
automatically decremented in order to speed up the MTIM timer and keep
precision better than 1.2%. The MTIM register and all the relevant registers are
H
processor block
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Figure 93
MCRA register
MCRA register
Z
MCRC register
SWA bit = 1 and
H
/Z
SC bit = 0
DCB bit
illustrates the process of updating the step ratio bits:
S
MWGHT [a
MZPRV [Z
MZREG [Z
MCOMP [C
Switched mode on page 214
n-1
n+1
8
n
]
]
n+1
(1)
]
(1)
A x B/256
]
(1)
8
n-1
S
), the successive value has to be
8
n
for more details).