st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 146

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
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Procedure
When a character is received:
Clearing the RDRF bit is performed by the following software sequence done by:
1.
2.
The RDRF bit must be cleared before the end of the reception of the next character to avoid
an overrun error.
Idle line
When an idle line is detected, there is the same procedure as a data received character plus
an interrupt if the ILIE bit is set and the I[|1:0] bits are cleared in the CCR register.
Overrun error
An overrun error occurs when a character is received when RDRF has not been reset. Data
can not be transferred from the shift register to the TDR register as long as the RDRF bit is
not cleared.
When an overrun error occurs:
The OR bit is reset by an access to the SCISR register followed by a SCIDR register read
operation.
Noise error
Oversampling techniques are used for data recovery by discriminating between valid
incoming data and noise.
When noise is detected in a character:
The NF bit is reset by a SCISR register read operation followed by a SCIDR register read
operation.
Select the M bit to define the word length.
Select the desired baud rate using the SCIBRR and the SCIERPR registers.
Set the RE bit, this enables the receiver which begins searching for a start bit.
The RDRF bit is set. It indicates that the content of the shift register is transferred to the
RDR.
An interrupt is generated if the RIE bit is set and the I[1:0] bits are cleared in the CCR
register.
The error flags can be set if a frame error, noise or an overrun error has been detected
during reception.
Accessing the SCISR register
Reading the SCIDR register.
The OR bit is set.
The RDR content is not lost.
The shift register is overwritten.
An interrupt is generated if the RIE bit is set and the I[|1:0] bits are cleared in the CCR
register.
The NF bit is set at the rising edge of the RDRF bit.
Data is transferred from the shift register to the SCIDR register.
No interrupt is generated. However this bit rises at the same time as the RDRF bit
which itself generates an interrupt.
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