st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 303

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
11
11.1
The CPU features 17 different addressing modes which can be classified in 7 main groups:
Table 177. CPU addressing mode groups
The CPU instruction set is designed to minimize the number of bytes required per instruction: To do so,
most of the addressing modes may be subdivided in two sub-modes called long and short:
The ST7 assembler optimizes the use of long and short addressing modes.
Table 178. CPU addressing mode overview
Addressing mode
Inherent
Immediate
Direct
Indexed
Indirect
Relative
Bit operation
Inherent
Immediate
Short
Long
No Offset
Short
Long
Short
Long
Short
Long
Relative
Long addressing mode is more powerful because it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cycles.
Short addressing mode is less powerful because it can generally only access page zero (0000h -
00FFh range), but the instruction size is more compact, and faster. All memory to memory
instructions use short addressing modes only (CLR, CPL, NEG, BSET, BRES, BTJT, BTJF, INC,
DEC, RLC, RRC, SLL, SRL, SRA, SWAP)
Mode
Direct
Direct
Direct
Direct
Direct
Indirect
Indirect
Indirect Indexed ld A,([$10],X)
Indirect Indexed ld A,([$10.w],X)
Direct
Instruction set
CPU addressing modes
Indexed ld A,(X)
Indexed ld A,($10,X)
Indexed ld A,($1000,X)
nop
ld A,#$55
ld A,$10
ld A,$1000
ld A,[$10]
ld A,[$10.w]
jrne loop
Syntax
00..FF
0000..FFFF
00..FF
00..1FE
0000..FFFF
00..FF
0000..FFFF
0000..FFFF
00..1FE
PC+/-127
Destination
Example
nop
ld A,#$55
ld A,$55
ld A,($55,X)
ld A,([$55],X)
jrne loop
bset
byte,#5
00..FF
00..FF
00..FF
00..FF
Pointer address
(Hex.)
byte
word
byte
word
Pointer size
(Hex.)
Instruction set
+ 0
+ 1
+ 2
+ 0
+ 1
+ 2
+ 2
+ 1
+ 2
+ 2
+ 2
+ 1
Length
(bytes)
303/371