st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 161

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
Note:
Note:
Note:
LIN reception
In LIN mode the reception of a byte is the same as in SCI mode but the LINSCI has features
for handling the LIN header automatically (identifier detection) or semiautomatically (synch
break detection) depending on the LIN header detection mode. The detection mode is
selected by the LHDM bit in the SCICR3.
Additionally, an automatic resynchronization feature can be activated to compensate for any
clock deviation, for more details please refer to
LIN header handling by a slave
Depending on the LIN header detection method the LINSCI signals the detection of a LIN
header after the LIN synch break or after the identifier has been successfully received.
It is recommended to combine the header detection function with mute mode. Putting the
LINSCI in mute mode allows the detection of headers only and prevents the reception of any
other characters.
This mode can be used to wait for the next header without being interrupted by the data
bytes of the current message in case this message is not relevant for the application.
Synch break detection (LHDM = 0)
When a LIN synch break is received:
In LIN slave mode, the FE bit detects all frame error which does not correspond to a break.
Identifier detection (LHDM = 1)
This case is the same as the previous one except that the LHDF and the RDRF flags are set
only after the entire header has been received (this is true whether automatic
resynchronization is enabled or not). This indicates that the LIN identifier is available in the
SCIDR register.
During LIN synch field measurement, the SCI state machine is switched off: No characters
are transferred to the data register.
LIN slave parity
In LIN slave mode (LINE and LSLV bits are set) LIN parity checking can be enabled by
setting the PCE bit.
In this case, the parity bits of the LIN identifier field are checked. The identifier character is
recognized as the third received character after a break character (included) (see
Figure
The RDRF bit in the SCISR register is set. It indicates that the content of the shift
register is transferred to the SCIDR register, a value of 0x00 is expected for a break.
The LHDF flag in the SCICR3 register indicates that a LIN synch break field has been
detected.
An interrupt is generated if the LHIE bit in the SCICR3 register is set and the I[1:0] bits
are cleared in the CCR register.
Then the LIN synch field is received and measured.
–
–
66).
If automatic resynchronization is enabled (LASE bit = 1), the LIN synch field is not
transferred to the shift register: There is no need to clear the RDRF bit.
If automatic resynchronization is disabled (LASE bit = 0), the LIN synch field is
received as a normal character and transferred to the SCIDR register and RDRF is
set.
LIN baud rate on page
On-chip peripherals
165.
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