st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 363

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
15.3.2
15.4
15.4.1
Workaround
Disable the timer interrupt before disabling the timer. While enabling, first enable the timer,
then enable the timer interrupts.
Perform the following to disable the timer
Perform the following to enable the timer again
LINSCI limitations
LINSCI wrong break duration
SCI mode
A single break character is sent by setting and resetting the SBK bit in the SCICR2 register.
In some cases, the break character may have a longer duration than expected:
In the same way, as long as the SBK bit is set, break characters are sent to the TDO pin.
This may lead to generate one break more than expected.
Occurrence
The occurrence of the problem is random and proportional to the baudrate. With a transmit
frequency of 19200 baud (f
occurrence is around 1%.
Workaround
If this wrong duration is not compliant with the communication protocol in the application,
software can request that an Idle line be generated before the break character. In this case,
the break duration is always correct assuming the application is not doing anything between
the idle and the break. This can be ensured by temporarily disabling interrupts.
The exact sequence is:
LIN mode
If the LINE bit in the SCICR3 is set and the M bit in the SCICR1 register is reset, the LINSCI
is in LIN master mode. A single break character is sent by setting and resetting the SBK bit
in the SCICR2 register. In some cases, the break character may have a longer duration than
expected:
TACR1 = 0x00h; // Disable the compare interrupt.
TACSR | = 0x40; // Disable the timer.
TACSR & = ~0x40; // Enable the timer.
TACR1 = 0x40; // Enable the compare interrupt.
20 bits instead of 10 bits if M = 0
22 bits instead of 11 bits if M = 1.
Disable interrupts
Reset and set TE (IDLE request)
Set and reset SBK (break request)
Re-enable interrupts
24 bits instead of 13 bits
CPU
= 8 MHz and SCIBRR = 0xC9), the wrong break duration
Known limitations
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