st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 176

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st7pmc2s6

Manufacturer Part Number
st7pmc2s6
Description
8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
Manufacturer
STMicroelectronics
Datasheet
On-chip peripherals
10.5.11
Caution:
176/371
LIN divider (LDIV) registers
LDIV is coded using the two registers LPR and LPFR. In LIN slave mode, the LPR register is
accessible at the address of the SCIBRR register and the LPFR register is accessible at the
address of the SCIETPR register.
LIN prescaler register (LPR)
Table 72.
Table 73.
LPR and LPFR registers have different meanings when reading or writing to them.
Consequently bit manipulation instructions (BRES or BSET) should never be used to modify
the LPR[7:0] bits, or the LPFR[3:0] bits.
LIN prescaler fraction register (LPFR)
Table 74.
LPR
7:0 LPR[7:0]
LPFR
7:4
3:0 LPFR[3:0]
Bit
Bit
7
7
Name
Name
-
LPR[7:0]
FEh
FFh
00h
01h
LPR register description
LIN mantissa rounded values
LPFR register description
-
LIN prescaler (mantissa of LDIV)
Reserved
Fraction of LDIV
These 8 bits define the value of the mantissa of the LDIV (see
6
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
These 4 bits define the fraction of the LDIV (see
Reserved
-
5
5
4
4
LPR[7:0]
R/W
Rounded mantissa (LDIV)
Function
Function
3
3
SCI clock disabled
254
255
1
-
Table
2
2
Reset value: 0000 0000 (00h)
LPFR[3:0]
Reset value: 0000 0000 (00h)
R/W
75).
Table
1
1
73).
0
0

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