st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 264

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st7pmc2s6

Manufacturer Part Number
st7pmc2s6
Description
8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
Manufacturer
STMicroelectronics
Datasheet
On-chip peripherals
264/371
Interrupt status register (MISR)
Table 125. MISR register description
MISR
Bit Name
7
6
5
4
3
2
R/W
PUI
7
RMI
PUI
RPI
CLI
EI
ZI
PWM update interrupt flag
Ratio increment interrupt flag
Ratio decrement interrupt flag
Current limitation interrupt flag
Emergency stop interrupt flag
BEMF zero-crossing interrupt flag
This bit is set by hardware when all the PWM compare register are transferred from
the preload to the active registers. The corresponding interrupt allows the user to
refresh the preload registers before the next PWM update event defined with MREP
register.
0: No PWM update interrupt pending
1: PWM update interrupt pending
Autoswitched mode (Swa bit = 1)
0: No R+ interrupt pending
1: R+ interrupt pending
Switched mode (Swa bit = 0)
0: No R+ action
1: The hardware increments the ST[3:0] bits when the next commutation occurs and
shifts all timer registers right.
Speed sensor mode (SWA bit = x, TES[1:0] bits = 01, 10, 11)
0: No R+ interrupt pending
1: R+ Interrupt pending
Autoswitched mode (SWA bit = 1)
0: No R- interrupt pending
1: R- Interrupt pending
Switched mode (SWA bit = 0)
0: No R- action
1: The hardware decrements the ST[3:0] bits when the next commutation occurs and
shifts all timer registers left
Speed sensor mode (SWA bit = x, TES[1:0] bits = 01, 10, 11)
0: No R- interrupt pending
1: R- Interrupt pending
0: No current limitation interrupt pending
1: Current limitation interrupt pending
0: No emergency stop interrupt pending
1: Emergency stop interrupt pending
0: No BEMF zero-crossing interrupt pending
1: BEMF zero-crossing interrupt pending
R/W
RPI
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
R/W
RMI
5
R/W
CLI
4
Function
R/W
EI
3
R/W
ZI
2
Reset value: 0000 0000 (00h)
R/W
DI
1
R/W
CI
0

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