st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 122

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
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Table 51.
Control/status register (CSR)
The 3 least significant bits are not used.
Table 52.
CSR
Bit
Bit Name
1
0
7
6
5
4
ICF1
RO
7
OCF1
ICF1
ICF2
TOF
EXEDG
IEDG2
Name
Input capture flag 1
Output compare flag 1
Timer overflow flag
Input capture flag 2
CR2 register description (continued)
CSR register description
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
Note: reading or writing the ACLR register does not clear TOF.
0: No input capture (reset value)
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR
OCF1
Input edge 2
External clock edge
RO
OC2R value in PWM mode. To clear this bit, first read the SR register, then read or
write the low byte of the IC1R (IC1LR) register.
register. To clear this bit, first read the SR register, then read or write the low byte of
the OC1R (OC1LR) register.
read the SR register, then read or write the low byte of the CR (CLR) register.
register, then read or write the low byte of the IC2R (IC2LR) register.
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
This bit determines which type of level transition on the ICAP2 pin triggers the
capture.
0: A falling edge triggers the capture
1: A rising edge triggers the capture
This bit determines which type of level transition on the external clock pin EXTCLK
triggers the counter register.
0: A falling edge triggers the counter register
1: A rising edge triggers the counter register
TOF
RO
5
ICF2
RO
4
Function
OCF2
Function
RO
3
TIMD
RO
2
Reset value: 0000 0000 (00h)
1
Reserved
-
0