st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 174

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
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SCI control register 3 (SCICR3)
Table 71.
SCICR3
6:5 LINE, LSLV
Bit
7
4
LDUM
R/W
7
LDUM
Name
LASE
SCICR3 register description
6
LIN divider update method
LIN mode enable bits
LIN auto synch enable
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
LINE, LSLV
This bit is set and cleared by software and is also cleared by hardware (when
RDRF = 1). It is only used in LIN slave mode. It determines how the LIN divider
can be updated by software.
0: LDIV is updated as soon as LPR is written
1: LDIV is updated at the next received character (when RDRF = 1)
Notes:
- If no write to LPR is performed between the setting of LDUM bit and the
- After LDUM has been set, it is possible to reset the LDUM bit by software.
These bits configure the LIN mode:
0x: LIN mode disabled
10: LIN master mode
11: LIN slave mode
The LIN master configuration enables the cabability to send LIN synch breaks
(13 low bits) using the SBK bit in the SCICR2 register.
The LIN slave configuration enables:
The LIN slave baud rate generator. The LIN divider (LDIV) is then represented by
Management of LIN headers
LIN synch break detection (11-bit dominant)
LIN wake-up method (see LHDM bit) instead of the normal SCI wake-up method
Inhibition of break transmission capability (SBK has no effect)
LIN parity checking (in conjunction with the PCE bit)
This bit enables the auto synch unit (ASU). It is set and cleared by software. It is
only usable in LIN slave mode.
0: Auto synch unit disabled
1: Auto synch unit enabled
reception of the next character, LDIV is updated with the old value.
In this case, LDIV can be modified by writing into LPR/LPFR registers.
the LPR and LPFR registers. The LPR and LPFR registers are read/write
accessible at the address of the SCIBRR register and the address of the
SCIETPR register.
(if no auto synchronization update occurs at the same time)
after a write to the LPR register
R/W
5
LASE
R/W
4
LHDM
R/W
Function
3
LHIE
R/W
2
Reset value: 0000 0000 (00h)
LHDF
R/W
1
R/W
LSF
0