st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 45

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
6.4
6.4.1
Note:
Caution:
6.4.2
Reset sequence manager (RSM)
Introduction
The reset sequence manager includes three reset sources are shown in
A reset can also be triggered following the detection of an illegal opcode or prebyte code.
Refer to
These sources act on the RESET pin and it is always kept low during the delay phase.
The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory
map.
The basic reset sequence consists of three phases as shown in
When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is
not programmed. For this reason, it is recommended to keep the RESET pin in low state
until programming mode is entered, in order to avoid unwanted behavior.
The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that
recovery has taken place from the reset state. The shorter or longer clock cycle delay
should be selected by option byte to correspond to the stabilization time of the external
oscillator used in the application.
The reset vector fetch phase duration is 2 clock cycles.
Figure 10. Reset sequence phases
Asynchronous external RESET pin
The RESET pin is both an input and an open-drain output with integrated R
resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It
can be pulled low by external circuitry to reset the device. See
characteristics
A reset signal originating from an external source must have a duration of at least t
in order to be recognized (see
MCU can enter reset state even in Halt mode.
External RESET source pulse
Internal LVD reset (low voltage detection)
internal watchdog reset
Active phase depending on the reset source
256 or 4096 CPU clock cycle delay (selected by option byte)
Reset vector fetch
Section 11.2.2 on page 309
for more details.
Active phase
Figure
for further details.
12). This detection is asynchronous and therefore the
256 or 4096 clock cycles
Reset
Internal reset
Section 12: Electrical
Figure
Supply, reset and clock
Fetch
vector
10.
Figure
ON
weak pull-up
11.
h(RSTL)in
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