st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 134

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
Note:
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Clearing the WCOL bit is done through a software sequence (see
Figure 59. Clearing the WCOL bit (write collision flag) software sequence
1.
Single master and multimaster configurations
There are two types of SPI systems:
Single master system
A typical single master system may be configured using a device as the master and four
devices as slaves (see
The master device selects the individual slave devices by using four pins of a parallel port to
control the four SS pins of the slave devices.
The SS pins are pulled high during reset since the master device ports are forced to be
inputs at that time, thus disabling the slave devices.
To prevent a bus conflict on the MISO line, the master allows only one active slave device
during a transmission.
For more security, the slave device may respond to the master with the received data byte.
Then the master receives the previous byte back from the slave device if all MISO and MOSI
pins are connected and the slave has not written to its SPIDR register.
Other transmission security methods can use ports for handshake lines or data bytes with
command fields.
Multimaster system
A multimaster system may also be configured by the user. Transfer of master control could
be implemented using a handshake method through the I/O ports or by an exchange of
code messages through the serial peripheral interface system.
The multimaster system is principally handled by the MSTR bit in the SPICR register and
the MODF bit in the SPICSR register.
Writing to the SPIDR register instead of reading it does not reset the WCOL bit.
Single master system
Multimaster system
Clearing sequence before SPIF = 1 (during a data byte transfer)
Clearing sequence after SPIF = 1 (end of a data byte transfer)
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
2nd step
1st step
Figure
Read SPICSR
Read SPIDR
60).
2nd step
1st step
WCOL = 0
SPIF = 0
Result
Read SPICSR
Read SPIDR
Figure
WCOL = 0
Result
59).