st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 152

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

On-chip peripherals
10.5.8
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These events generate an interrupt if the corresponding enable control bit is set and the
interrupt mask in the CC register is reset (RIM instruction).
SCI mode registers
SCI status register (SCISR)
1. This bit has a different function in LIN mode, please refer to
Table 62.
SCISR
Bit Name
7
6
5
4
TDRE
RO
RDRF
TDRE
7
IDLE
TC
Transmit data register empty
Transmission complete
Received data ready flag
Idle line detected
SCISR register description
This bit is set by hardware when the content of the TDR register has been transferred
into the shift register. An interrupt is generated if the TIE = 1 in the SCICR2 register. It
is cleared by a software sequence (an access to the SCISR register followed by a
write to the SCIDR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register
This bit is set by hardware when transmission of a character containing data is
complete. An interrupt is generated if TCIE = 1 in the SCICR2 register. It is cleared by
a software sequence (an access to the SCISR register followed by a write to the
SCIDR register).
0: Transmission is not complete
1: Transmission is complete
Note: TC is not set after the transmission of a preamble or a break.
This bit is set by hardware when the content of the RDR register has been transferred
to the SCIDR register. An interrupt is generated if RIE = 1 in the SCICR2 register. It is
cleared by a software sequence (an access to the SCISR register followed by a read
to the SCIDR register).
0: Data is not received
1: Received data is ready to be read
This bit is set by hardware when an idle line is detected. An interrupt is generated if
the ILIE = 1 in the SCICR2 register. It is cleared by a software sequence (an access to
the SCISR register followed by a read to the SCIDR register).
0: No idle line is detected
1: Idle line is detected
Note: The idle bit is not set again until the RDRF bit has been set itself (that is, a new
idle line occurs).
RO
TC
6
ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
RDRF
RO
5
IDLE
RO
4
Function
OR
RO
3
Section 10.5.10: LIN mode
(1)
NF
RO
2
(1)
Reset value: 1100 0000 (C0h)
FE
RO
registers.
1
(1)
PE
RO
0
(1)