st7pmc2s6 STMicroelectronics, st7pmc2s6 Datasheet - Page 53

• Manufacturer Part Number: st7pmc2s6
• Description: 8-bit Mcu For Automotive With Nested Interrupts, Flash, 10-bit Adc, Brushless Motor Control, 5 Timers, Spi, Linsci?
• Manufacturer: STMicroelectronics

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto
6.5.6
System integrity control/status register (SICSR, page 1)
Table 10.
SICSR, page 1
Bit
7
6
5
4
3
2
1
0
PAGE
R/W
VCOEN
7
PLLEN
CKSEL
Name
LOCK
PAGE
-
-
-
Reserved
SICSR (page 1) register description
SICSR register page selection
Reserved, must be kept cleared
VCO enable
PLL locked
PLL enable
Reserved, must be kept cleared.
Clock source selection
Reserved, must be kept cleared
This bit selects the SICSR register page. It is set and cleared by software.
0: Access to SICSR register mapped in page 0
1: Access to SICSR register mapped in page 1
This bit is set and cleared by software.
0: VCO (voltage controlled oscillator) connected to the output of the PLL charge
1: VCO tied to ground in order to obtain a 10 MHz frequency (f
Note: During ICC session, this bit is set to 1 in order to have an internal frequency
which does not depend on the input clock. Then, it can be reset in order to run faster
with an external oscillator.
This bit is read only. It is set by hardware. It is set automatically when the PLL
reaches its operating frequency.
0: PLL not locked
1: PLL locked
This bit enables the PLL and the clock detector. It is set and cleared by software.
0: PLL and clock detector (CKD) disabled
1: PLL and clock detector (CKD) enabled
Notes:
- During ICC session, this bit is set to 1.
- PLL cannot be disabled if the PLL clock source is selected (CKSEL = 1).
This bit selects the clock source: oscillator clock or clock from the PLL. It is set and
cleared by software. It can also be set by option byte (PLL opt).
0: Oscillator clock selected
1: PLL clock selected
Notes:
- During ICC session, this bit is set to 1. Then, CKSEL can be reset in order to run
- Clock from the PLL cannot be selected if the PLL is disabled (PLLEN = 0).
- f the clock source is selected by PLL option bit, CKSEL bit selection has no effect.
6
with f
-
pump (default mode), to obtain a 16 MHz output frequency (with an 8 MHz input
frequency)
OSC
VCOEN
.
R/W
5
LOCK
RO
4
Function
PLLEN
R/W
3
Reserved
2
-
Reset value: 0000 0000 (00h)
Supply, reset and clock
CKSEL
vco
R/W
1
)
Reserved
0
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