tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 109

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.2.2
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Wait Timing
A[23:16]
AD[15:0]
ALE
RD
WAIT
The CS/Wait Controller provides two ways to insert wait states in a bus cycle.
Each address block can be programmed either:
A[23:16]
AD[15:0]
ALE
RD
to insert required number of wait state cycles (up to seven cycles), or
to use the WAIT pin to insert wait states dynamically on a cycle basis
Figure 8.3 Read Cycle Timing (with Zero and One Wait State Cycle)
Following are bus cycle timing diagrams with wait states.
Figure 8.4 Read Cycle Timing (with 1 + N Wait States; N=1)
tsys
tsys
ADR
ADR
Upper Address
0 Wait State
Upper Address
0 Wait State
DATA
DATA
TMP1941AF-69
ADR
ADR
1 Wait State
Wait State
(1 + N Wait States; N = 1)
Upper Address
Wait States
Upper Address
DATA
DATA
TMP1941AF
2003-03-27