tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 184

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

TB3MOD
(0xFFFF_F1B2)
Name
Read/Write
Reset Value
Function
Must be written as 00.

7
0
Figure 12.10 TMRB3 Mode Register
R/W

6
0
TMRB3 Mode Register
TMP1941AF-144
Software
capture
0: Capture
1: Don’t
TB3CP0
care
Up-counter (UC3) clear control
Capture triggers
Software capture
W*
5
1
00
01
10
11
0
1
0
1
Capture triggers
00: Disabled
01: Disabled
10: Disabled
11: TA1OUT↑TA1OUT↓
Disabled
UC3 is reset upon a match with TB3RG1.
Capture disabled
Capture disabled
Capture disabled
Latches UC3 value into TB3CP0 at rising edges of TA1OUT.
Latches UC3 value into TB3CP1 at falling edges of TA1OUT.
Latches UC3 value into TB3CP0.
Don’t care
TB3CPM1 TB3CPM0
4
0
3
0
UC3 clear
control
0: Disable
1: Enable
TB3CLE
R/W
2
0
TMP1941AF
TMRB3 clock source
00: TB3IN0 input
01: φT1
10: φT4
11: φT16
TB3CLK1
1
0
2003-03-27
TB3CLK0
0
0