tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 138

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(3) Transfer Request Generation
(4) Data Transfer Modes
(5) DMA Channel Operation
the Str bit in the CCRn register is set. The channel immediately requests the bus and begins
transferring data.
(INTDREQn) must be asserted by the Interrupt Controller before the channel requests the bus and
begins a transfer. Although INTDREQn can be programmed for level/edge sensitivity, the
TMP1941AF requires INTDREQn to be low-level sensitive.
memory and an I/O peripheral. In this mode, the DMAC explicitly addresses both the source and
destination devices. The DMAC also generates a DACKn signal when accessing an I/O
peripheral.
destination write cycle. In the source read cycle, the data being transferred is read from the source
address and put into the DMAC internal Data Holding Register (DHR). In the destination write
cycle, the DMAC writes data in the DHR to a destination address.
(n = 0−3) enables a particular channel and puts it in Ready state.
the bus and begins a transfer. When no DMA request is pending, the DMAC relinquishes the bus
to the TX19 core processor and returns to Ready state. The channel can terminate by normal
completion or from an error of a bus cycle. When a channel terminates, that channel is put in Idle
state. Interrupts can be generated by error termination or by normal channel termination.
Each DMA channel supports two types of request generation methods: internal and external.
Internal requests are those generated within the DMAC. The DMA channel is started as soon as
If a channel is programmed for external request and the Str bit is set, the transfer request signal
The TMP1941AF DMAC supports dual-address transfers, but not single-address transfers.
The dual-address mode allows data to be transferred from memory to memory and between
In dual-address mode, a transfer takes place in two DMA bus cycles: a source read cycle and a
The DMAC has four independent DMA channels 0 to 3. Setting the Start (Str) bit in the CCRn
When a DMA request is detected in any of the channels in Ready state, the DMAC arbitrates for
Figure 10.11shows a general state transitions of a DMA channel.
Idle
Figure 10.11 DMA Channel State Transitions
Transfer done
Start
TMP1941AF-98
up bus mastership.
The DMAC gives
Transfer
Ready
The DMAC assumes
bus mastership.
The DMAC does not
have bus mastership.
The DMAC has bus
mastership.
TMP1941AF
2003-03-27