tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 166

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

the duty cycle) can be changed dynamically by writing a new value into the register buffer. Upon a 2
counter overflow, the TA0REG latches a new value from the register buffer.
signal with variable duty cycle.
In 8-bit PWM generation mode, if the double-buffering function is enabled, the TA0REG value (i.e.,
The TA0REG can be loaded with a new value upon every counter overflow, thus generating a PWM
Example: Generating a PWM signal as shown below on the TA1OUT pin (fc = 40 MHz)
X = Don’t care,
TA01RUN
TA01MOD
TA0REG
TA1FFCR
P7CR
P7FC
TA01RUN
Match Between TA0REG
Clocking conditions:
Under the above conditions, φT1 has a 0.2-µs period (@fc = 40 MHz).
which is equal to 2
Hence, the time constant value to be programmed into the TA0REG is 48H.
System clock:
High-speed clock gear: ¤1 (fc)
Prescaler clock:
and Up-Counter 0
25.4 µs ÷ 0.2 µs = 127
14 µs ÷ 0.2 µs = 70 = 46H
(Compare Value)
Register Buffer
2
n
-1 Overflow
MSB
←
←
←
←
←
←
←
TA0REG
– = No change
7
−
1
0
X
−
−
1
Figure11.17 Register Buffer Operation
6
X
1
1
X
−
−
X
14 µs
25.4 µs
7
– 1.
5
X
1
0
X
−
−
X
4
X
0
0
X
−
−
X
TMP1941AF-126
Up-Counter = Q
High-speed (fc)
fperiph/4 (fperiph = fsys)
3
−
−
0
1
−
−
−
2
−
−
1
0
−
−
1
Q
Q
1
−
0
1
1
1
1
−
1
2
LSB
0
0
1
0
X
−
−
1
1
Stops and clears the TMRA0.
Selects 8-bit PWM mode (period = 2
the clock source.
Writes 46H.
Clears the TA1FF to 0 and enables toggling.
Configures P71 as the TA1OUT output pin.
Starts the TMRA0.
Shift into TA0REG
Up-Counter = Q
TMP1941AF
Q
Write to TA0REG
(Register Buffer)
2
2
Q
3
7
−1) and φT1 as
2003-03-27
n
-1