tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 211
tmp1941af
Manufacturer Part Number
tmp1941af
Description
32-bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP1941AF.pdf
(354 pages)
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13.2.12 Signal Generation Timing
(1) UART Mode
(2) I/O Interface Mode
Receive Operation
Transmit Operation
Interrupt
Framing Error
Parity Error
Overrun Error
Interrupt
Transmit
Interrupt
Receive Interrupt
Note 1:
Note 2:
Don’t modify any control register during transmit or receive operations.
Don’t disable receive operations by clearing the SC0MOD0.RXE bit while any character is
being received.
SCLK Output Mode
SCLK Input Mode
SCLK Output Mode
SCLK Input Mode
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., bit 8)
Immediately before
the stop bit is shifted
out
9 Data Bits
9 Data Bits
TMP1941AF-171
Immediately after the rising edge of the last SCLK pulse (See Figure
13.29)
Immediately after the rising or falling edge of the last SCLK pulse,
as programmed (See Figure 13.30)
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.31)
When a received character has been transferred to Receive Buffer
2 (SC0BUF) (i.e., immediately after the last SCLK pulse) (See
Figure 13.32)
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., parity bit)
Middle of the last bit
(i.e., parity bit)
Immediately before the
stop bit is shifted out
8 Data Bits with
8 Data Bits with
Parity
Parity
Immediately before the stop bit
is shifted out
Middle of the stop bit
Middle of the stop bit
Middle of the last bit
(i.e., parity bit)
Middle of the stop bit
8 Data Bits with No Parity
7 Data Bits with No Parity
8 Data Bits with No Parity
7 Data Bits with No Parity
7 Data Bits with Parity
7 Data Bits with Parity
TMP1941AF
2003-03-27
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