tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 177

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12.2.5
Capture Control Logic
(TB0CP0 and TB0CP1). The TB0CPM[1:0] field in the TB0MOD register selects a capture trigger
input to be sensed by the capture control logic.
TB0MOD.TB0CP0 bit causes the current UC0 value to be latched into the TB0CP0. To use the capture
capability, the prescalar must be running (i.e., TB0RUN.TB0PRUN=1).
Note 1: Reading the eight low-order bits of a capture register disables the capture capability. Reading the
Note 2: Don’t stop the timer after only reading the eight low-order bits of a capture register. If this is done,
Note 3: When the TB0IN0 pin is selected as a capture trigger input, it can not function as a timer clock
The Capture registers are read-only registers and cannot be written by software.
The capture control logic controls the capture of an up-counter (UC0) value into the capture registers
Futhermore, a counter value can be captured under software control; a write of 0 to the
TMRB0
TMRB1
TMRB2
TMRB3
8 high-order bits
8 high-order bits
8 high-order bits
8 high-order bits
0xFFFF_F18D
0xFFFF_F19D
0xFFFF_F1AD
0xFFFF_F1BD
eight high-order bits thereafter re-enables the capture capability. The reading of a whole capture
register should be completed during an interval between active transitions on the defined capture
trigger input.
the capture capability continues to remain in the disabled state even after the timer is restarted.
source.
TB0CP0
TB1CP0
TB2CP0
TB3CP0
8 low-order bits
8 low-order bits
8 low-order bits
8 low-order bits
0xFFFF_F18C
0xFFFF_F19C
0xFFFF_F1AC
0xFFFF_F1BC
TMP1941AF-137
8 high-order bits
8 high-order bits
8 high-order bits
8 high-order bits
0xFFFF_F1AF
0xFFFF_F1BF
0xFFFF_F18F
0xFFFF_F19F
TB0CP1
TB1CP1
TB2CP1
TB3CP1
8 low-order bits
8 low-order bits
8 low-order bits
8 low-order bits
0xFFFF_F1AE
0xFFFF_F1BE
0xFFFF_F18E
0xFFFF_F19E
TMP1941AF
2003-03-27