tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 207

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

13.2.3
13.2.4
13.2.5
13.2.6
Serial Clock Generator
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•
Receive Counter
SIOCLK. The receiver utilizes 16 clocks for each received bit, and oversamples each bit three times
around their center (with 7th to 9th clocks). The value of a bit is determined by voting logic which takes
the value of the majority of three samples. For example, if the three samples of a bit are 1, 0 and 1, then
that bit is interpreted as a 1; if the three samples of a bit are 0, 0 and 1, then that bit is interpreted as a 0.
Receive Controller
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•
Receive Buffer
by bit into Receive Buffer 1. When a whole character (i.e., 7 or 8 bits, as programmed) is loaded into
Receive Buffer 1, it is transferred to Receive Buffer 2 (SC0BUF), and a receive-done interrupt
(INTRX0) is generated.
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•
This block generates a basic clock (SIOCLK) that controls the transimit and receive circuit.
The receive counter is a 4-bit binary up-counter used in UART mode. This counter is clocked by
The receive buffer is double-buffered to prevent overrun errors. Received data is serially shifted bit
I/O Interface Mode
clock from the baud rate generator is divided by two to generate the SIOCLK clock. When the
SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the external SCLK0 clock
is used as the SIOCLK clock; the SC0CR.SCLKS bit determines the active clock edge.
UART Mode
clock (fsys/2), the trigger output signal from the 8-bit timer TMRA0, and the external SCLK0
clock, according to the setting of the SC0MOD0.SC[1:0] field.
I/O Interface Mode
controller samples the RXD0 input at the rising edge of the shift clock driven out from the SCLK0
pin. If the SCLK0 pin is configured as an input by setting the SC0CR.IOC bit to 1, the receive
controller samples the RXD0 input at either the rising or falling edge of the SCLK0 clock, as
programmed in the SC0CR.SCLKS bit.
UART Mode
receive controller begins sampling the incoming data streams. The start bit, each data bit and the
stop bit are sampled three times for 2-of-3 majority voting.
I/O Interface Mode
details, refer to Section 13.4.
UART Mode
new character through the RXD0 pin before the CPU picks up the previous character in Receive
Buffer 2. However, the CPU must read Receive Buffer 2 before Receive Buffer 1 is filled with a
new character. Otherwise, an overrun error occurs, causing the character previouly in Receive
Buffer 1 to be lost. Even in that case, the contents of Receive Buffer 2 and the SC0CR.RB8 bit are
preserved.
When the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the output
The SIOCLK clock is selected from a clock produced by the baud rate generator, the system
If the SCLK0 pin is configured as an output by clearing the SC0CR.IOC bit to 0, the receive
The receive controller contains the start bit detection logic. Once a valid start bit is detected, the
The double-buffer structure can be used in full-duplex mode, but not in half-duplex mode. For
The CPU reads a character from Receive Buffer 2 (SC0BUF). Receive Buffer 1 can accept a
TMP1941AF-167
TMP1941AF
2003-03-27