tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 70

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

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core processor. Hardware interrupts are summarized below.
STOP/SLEEP wake-up signal (negative-edge triggered).
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INT0–INT4
INTRTC
INT0–INTA
On-Chip
Peripherals
The INTC collects interrupt events, prioritizes them and presents the highest-priority request to the TX19
Here are example register settings required to enable and disable the INT0 interrupt as a source of the
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External interrupts INT5–INTA and internal interrupts except INTRTC
Enabling the interrupt
Disabling the interrupt
IMCGA0.EMCG[01:00] = 10
EICRCG.ICRCG[2:0] = 000
IMCGA0.INT0EN = 1
IMC0L.EIM[11:10] = 01
INTCLR.EICLR[5:0] = 000001 : Clear INT0 request
IMC0L.IL[12:10] = 101
Status.IEc = 1, Status.CMask = xxx
Status.IEc = 0
IMC0L.IL[12:10] = 000
INTCLR.EICLR[5:0] = 000001 : Clear INT0 request
IMCGA0.INT0EN = 0
EICRCG.ICRCG[2:0] = 000
These interrupts are programmable through the INTC.
Interrupt
defines the interrupt polarity. The INTxEN bit in the IMCGxx register controls whether these
interrupt sources are enabled as wake-up signal sources (1=enable). If enabled, the interrupt
polarity (EIMxx) field in the INTC’s IMCxx register has no effect, but must be set to 01, or high
level. The ILxx field in the IMCxx register determines the action taken after exiting STOP/SLEEP
mode; i.e., whether execution resumes with an interrupt service routine.
When disabled for STOP/SLEEP wake-up signaling
polarity and enabling of these interrupt sources. INTRTC is programmed through both the CG and
INTC, regardless of whether it is used for wake-up signaling.
If INT0–INT4 are disabled for STOP/SLEEP wake-up signaling, the INTC alone determines the
INTDMAn
Other
IMCGxx reg. in CG
IMCx reg. in INTC
IMCGxx reg. in CG
IMCx reg. in INTC
IMCx reg. in INTC
IMCx reg. in INTC
IMCx reg. in INTC
Programming
: Configure INT0 as negative-edge triggered
: Clear INT0 request
: Enable INT0 for wake-up signaling
: Configure INT0 as high-level sensitive
: Set INT0 priority level to 5
: Disable INT0 interrupt
: Disable INT0 for wake-up signaling
: Clear INT0 request
TMP1941AF-30
When enabled for STOP/SLEEP wake-up signaling, the polarity
field in the INTC has no effect, but must always be set to “high-
level.” The actual sensitivity is programmed in the CG. When
disabled for STOP/SLEEP wake-up signaling, interrupt sensitivity
is programmed in the INTC. In either case, each interrupt source
is individually configurable as negative or positive polarity, and
as edge-triggered or level-sensitive.
In the INTC, the polarity must always be set to “high-level.” The
actual sensitivity must be configured as rising-edge triggered in
the CG.
Configurable as negative or positive polarity, and as edge-
triggered or level-sensitive.
Falling edge
Rising edge
Interrupt Sensing
TMP1941AF
TX19 core processor
TX19 core processor
CG block
INTC block
2003-03-27