tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 269

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

15.2.5
15.2.6
Conversion Time
conversion time of 8.6 µs with 10-MHz fadc. The A/D conversion clock can be selected from fsys/2,
fsys/4 and fsys/8 through the programming of the ADCCK[1:0] field in the ADCCLK register. To
assure conversion accuracy, conversion time must be no shorter than 8.6 µs.
Storing and Reading the A/D Conversion Result
ADREG37H/L). These registers are read-only.
ADREG37H/L sequentially. In other modes, channels AN0 and AN4 share the ADREG04H/L;
channels AN1 and AN5 share the ADREG15H/L; channels AN2 and AN6 share the ADREG26H/L;
and channels AN3 and AN7 share the ADREG37H/L.
registers.
The conversion process requires 86 conversion clocks per channel. For example, this results in a
Conversion results are loaded into conversion result high/low register pairs (ADREG04H/L to
In fixed-channel continuous conversion mode, conversion data goes into the ADREG04H/L to the
Table 15.4 shows the relationships between the analog input channels and the A/D conversion result
X = Don’t care
Fixed-Channel Single
Conversion Mode
Channel Scan Single
Conversion Mode
Fixed-Channel Continuous
Conversion Mode
Channel Scan Continuous
Conversion Mode
Conversion Clock
Table 15.2 Interrupt Request Generation in Each AD Conversion Mode
40 MHz
32 MHz
20 MHz
16 MHz
10 MHz
8 MHz
fsys
Mode
Table 15.3 Conversion Time
Don’t use.
Don’t use.
TMP1941AF-229
10.75 µs
fsys/2
17.2 µs
21.5 µs
After a conversion
After a scan conversion
sequence
After each conversion
After every four conversions
After each scan conversion
sequence
8.6 µs
Interrupt Request
Generation
10.75 µs
fsys/4
17.2 µs
21.5 µs
34.4 µs
43.0 µs
8.6 µs
ITM0
X
X
X
0
1
fsys/8
17.2 µs
21.5 µs
34.4 µs
43.0 µs
68.8 µs
86.0 µs
ADMOD0
REPEAT
TMP1941AF
0
0
1
1
SCAN
2003-03-27
0
1
0
1