tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 262

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADMOD0
(0xFFFF_F310)
15.1 Register Description
register pairs (ADREG04H/L, ADREG15H/L, ADREG26H/L, ADREG37H/L) and a clock select register
(ADCCLK). The conversion result registers contain the digital values of completed conversions. The clock
select register selects an A/D conversion clock.
The ADC has two mode control registers (ADMOD0 and ADMOD1), four conversion result high/low
Figure 15.2 to Figure 15.6 show the registers available in the ADC.
Name
Read/Write
Reset Value
Function
Note:
The EOCF bit is cleared when read.
End-of-
conversion
flag
0: Before or
1: Completed
during
conversion
EOCF
Figure 15.2 A/D Mode Control Register 0 (ADMOD0)
7
0
R
A/D
conversion
busy flag
0: Idle
1: During
conversion
ADBF
A/D Mode Control Register 0
6
0
TMP1941AF-222
Must be
written as 0.

5
0
Must be
written as 0.

4
0
Interrupt in fixed-channel continuous conversion mode
0
1
Interrupt
See below.
ITM0
Fixed-Channel Continuous Conversion Mode
SCAN = 0, REPEAT = 1
Generates INTAD interrupt when a single
conversion has been completed.
Generates INTAD interrupt when a sequence
of four conversions has been completed.
3
0
R/W
Continuous
conversion
mode
0: Single
1: Continuous
REPEAT
2
0
TMP1941AF
Channel
scan mode
0: Fixed-
1: Channel
SCAN
channel
scan
1
0
2003-03-27
A/D
conversion
start
0: Don’t
1: Start
This bit is
always read
as 0.
care
ADS
0
0