tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 193

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

X = Don’t care,
Example: Generating a one-shot pulse with a width of 2 ms and a delay of 3 ms on assertion of an
Settings in the main routine
TB0MOD
TB0FFCR
P7CR
P7FC
IMC2HL
IMC7LL
IMC7LH
TB0RUN
Settings in INT5
TB0RG0
TB0RG1
TB0FFCR
IMC7LH
Settings in INTTB01
TB0FFCR
IMC7LH
Clocking conditions:
System clock:
High-speed clock gear: ×1 (fc)
Prescaler clock:
external trigger pulse on the TB0IN0 pin
← X
← X
← −
← −
← X
← X
← X
← −
← TB0CP0 + 3ms/φT1
← TB0RG0 + 2ms/φT1
← X
← X
← X
← X
– = No change
7
6
X
X
1
1
X
X
X
0
X
X
X
X
5
1
0
−
−
1
1
1
X
−
1
−
1
4
0
0
−
−
1
1
1
X
−
1
−
1
TMP1941AF-153
High-speed (fc)
fperiph/4 (fperiph = fsys)
3
1
0
−
−
0
0
0
−
1
0
0
0
2
0
0
−
−
1
0
0
1
1
1
0
0
1
0
1
−
−
0
0
0
X
−
0
−
0
0
1
0
−
−
0
0
0
1
−
0
−
0
Places the counter in free-running mode.
Selects φT1 as the counter clock source.
Latches UC0 value into TB0CP0 at rising edges of
the TB0IN0 input.
Clears TB0FF0 to 0.
Disables the toggle-trigger for TB0FF0.
Configures the P76 pin as TB1OUT.
Enables INT5 and disables INTTB00 and INTTB01.
Starts the TMRB0.
Enables the TB0FF0 toggle-trigger for TB0RG0 and
TB0RG1 matches.
Enables INTTB01.
Disables the TB0FF0 toggle-trigger for TB0RG0 and
TB0RG1 matches.
Disables INTTB01.
TMP1941AF
2003-03-27