tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 291
tmp1941af
Manufacturer Part Number
tmp1941af
Description
32-bit Tx System Risc
Manufacturer
TOSHIBA Semiconductor CORPORATION
Datasheet
1.TMP1941AF.pdf
(354 pages)
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18.7.2
Transmit Data
Receive Data
SCK
(SO)
Clock-Synchronous 8-Bit SIO Mode
letter n denotes the value of n programmed into the SCK[2:0] (SCL output frequency select) field in the
SBI0CR1.
(1) SCK Input Mode
(2) SCK Output Mode
(SI)
SCK period
SO data to SCK rise
SO data hold after SCK rise
SI data valid to SCK rise
SI data hold after SCK rise
SCK period (programmable)
SO data to SCK rise
SO data hold after SCK rise
SI data valid to SCK rise
SI data hold after SCK rise
In the tables below, the letters x and T represent the fsys and φT0 cycle periods, respectively. The
The electrical specifications below are for an SCK signal with a 50% duty cycle.
Parameter
Parameter
t
t
OSS
SRD
VALID
0
t
0
SCY
TMP1941AF-251
tSCY
tOSS
tOHS
tSRD
tHSR
t
t
t
t
t
Symbol
Symbol
SCY
OSS
OHS
SRD
HSR
VALID
1
1
(tSCY/2) − (6x + 30)
t
HSR
(tSCY/2) + 4x
(t
(t
t
SCY
SCY
OHS
4x + 10
2x + 30
2
Min
Min
16x
n
Equation
Equation
/2) − 20
/2) − 20
0
0
× T
VALID
2
2
Max
Max
TMP1941AF
Min
Min
400
300
110
800
380
380
20
80
0
0
40 MHz
40 MHz
Max
Max
VALID
3
2003-03-27
3
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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