tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 174

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

12.2 Timer Components
12.2.1
Note 1: The prescaler's output clock φ φ φ φ Tn must be selected so that the relationship φ φ φ φ Tn < fsys/2 is satisfied.
Note 2: Do not change the clock gear value while the timer is running.
Note 3: The — character means “Don’t use.”
SYSCR1.FPSEL
Peripheral Clock
0 (gear)
Select
1 (fc)
Prescaler
prescalar clock source (φT0) can be selected from fperiph, fperiph/2 and fperiph/4 by programming the
PRCK[1:0] field of the SYSCR0 located within the CG. fperiph can be selected from fgear (geared
clock) and fc (non-geared clock) by programming the FPSEL bit of the SYSCR1 located within the CG.
A write of 1 to this bit starts the prescalar. A write of 0 to this bit clears and halts the prescalar.
12.2 shows prescalar output clock resolutions (@fc = 32 MHz).
The TMRB0 has a 5-bit prescalar that slows the rate of a clocking source to the counter. The
The TB0RUN bit in the TB0RUN register allows the enabling and disabling of the TMRB0 prescalar.
Prescalar output taps can be divide-by-2 (φT1), divide-by-8 (φT4) and divide-by-32 (φT16). Table
SYSCR1.GEAR[1:0]
Clock Gear Value
01 (fc/2)
10 (fc/4)
11 (fc/8)
01 (fc/2)
10 (fc/4)
11 (fc/8)
00 (fc)
00 (fc)
Table 12.2 Prescaler Output Clock Resolutions
SYSCR0.PRCK[1:0]
TMP1941AF-134
Prescaler Clock
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
00 (fperiph/4)
01 (fperiph/2)
10 (fperiph)
Source
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
3
4
3
5
4
6
3
3
2
5
2
φT1
Prescaler Output Clock Resolution
(0.1 µs)

(0.4 µs)
(0.2 µs)

(0.8 µs)
(0.4 µs)

(1.6 µs)
(0.8 µs)

(0.1 µs)

(0.2 µs)








(0.2 µs)
(0.2 µs)
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
5
4
3
6
5
4
7
6
5
8
7
6
5
4
3
5
4
3
5
4
5
φT4
(0.8 µs)
(0.4 µs)
(0.2 µs)
(1.6 µs)
(0.8 µs)
(0.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(0.4 µs)
(0.2 µs)
(0.8 µs)
(0.4 µs)
(0.2 µs)
(0.8 µs)
(0.4 µs)

(0.8 µs)


TMP1941AF
@fc = 40 MHz
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
fc/2
10
9
9
φT16
7
6
5
8
7
6
8
7
8
7
6
5
7
6
5
7
6
5
7
6
5
(12.8 µs)
(12.8 µs)
(25.6 µs)
2003-03-27
(3.2 µs)
(1.6 µs)
(0.8 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(6.4 µs)
(3.2 µs)
(6.4 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)
(3.2 µs)
(1.6 µs)
(0.8 µs)