tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 273

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2
When a counter overflow occurs, the WDT generates a WDT interrupt, as shown below.
programmed, a counter overflow causes the WDT to assert the internal reset signal for a 22- to 29-state time.
After a reset, the fsys clock is, by default, generated by dividing the high-speed oscillator clock (fc) by eight
through the clock gear function; the WDT clock source (fsys/2) is derived from this fsys clock.
15
The WDT contains a 22-stage binary counter clocked by the fsys/2 clock. This binary counter provides
Also, the counter overflow can be programmed to cause a system reset as the time-out action. If so
, 2
Note:
WDT Interrupt
Internal Reset
WDT Counter
WDT Interrupt
WDT Counter
(via software)
17
WDT Clear
, 2
19
The TMP1941AF continues sampling the PLLOFF pin during a reset operation caused by the WDT.
Therefore, the PLLOFF pin must be tied to either logic high or logic low.
or 2
21
as a counter overflow signal, as programmed into the WDTP[1:0] field in the WDMOD.
n
n
22–29 States (8.8–11.6 µs @ fc = 40 MHz, fsys = 5 MHz, fsys/2 = 2.5 MHz)
Figure 16.3 Reset Operation
TMP1941AF-233
Overflow
Figure 16.2 Default Operation
Overflow
A write of a special clear-count code
TMP1941AF
2003-03-27
0