tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 250

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

14.6.4
TRX
1
0
Generating a STOP Condition
clearing the BB bit in the same register causes the SBI to start a sequence for generating a STOP
condition on the I
the bus.
(high) again; when SCL is high, the SBI drives the SDA pin high to generate a STOP condition.
When the SBI0SR.BB bit is set, setting the MST, TRX and PIN bits in the SBI0CR2 to 1 and
If another device is holding down the SCL bus line, the SBI waits until the SCL line is released
AL
1
0
1
0
SBI0CR2 ← 1 1 0 1 1 0 0 0
AAS AD0
1
1
0
1
0
1
0
1 → MST
1 → TRX
0 → BB
1 → PIN
SCL Pin
SDA Pin
PIN Bit
BB Bit (read)
2
1/0
1/0
1/0
C bus. Do not alter the contents of these bits until the STOP condition is present on
0
0
0
0
Figure 14.17 Generating a STOP Condition
7 6 5 4 3 2 1 0
Arbitration was lost while the slave address
was being transmitted, and the SBI
received a slave address with the direction
bit set transmitted by another master.
In slave-receiver mode, the SBI received a
slave address with the direction bit set
transmitted by the master.
In slave-transmitter mode, the SBI has
completed a transmission of one data word.
Arbitration was lost while a slave address
was being transmitted, and received either a
slave address with the direction bit cleared
or a general-call address transmitted by
another master.
Arbitration was lost while a slave address
or a data word was being transmitted, and
the transfer terminated.
In slave-receiver mode, the SBI received
either a slave address with the direction bit
cleared or a general-call address
transmitted by the master.
In slave-receiver mode, the SBI has
completed a reception of a data word.
Table 14.2 Processing in Slave Mode
TMP1941AF-210
State
Generate a STOP condition.
STOP Condition
Set the SBI0CR1.BC[2:0] field to the
number of bits in a data word and write the
transmit data into the SBI0DBR.
Test the SBI0SR.LRB bit. If the LRB bit is
set, that means the master-receiver does
not require further data. Set the
SBI0CR2.PIN bit to 1 and clear the TRX bit
to 0 to release the bus.
If the LRB bit is cleared, that means the
master-receiver requires further data. Set
the SBI0CR1.BC[2:0] field to the number of
bits in the data word and write the transmit
data to the SBI0DBR.
Read the SBI0DBR (a dummy read) to set
the SBI0CR2.PIN bit to 1, or write a 1 to
this bit.
Set the SBI0CR1.BC[2:0] field to the
number of bits in the data word and read
the received data from the SBI0DBR.
TMP1941AF
Processing
2003-03-27