tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 56

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

ADCCLK
(0xFFFF_EE04)
IMCGA0
(0xFFFF_EE10)
IMCGA1
(0xFFFF_EE11)
IMCGA2
(0xFFFF_EE12)
5.2.2
5.2.3
ADC Conversion Clock
STOP/SLEEP Wake-up Interrupt Control Registers (INTCG Registers)
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Name
Read/Write
Reset Value
Function
Note: A/D conversion is executed using the clock selected by this register. Reduced conversion
Note: The conversion clock must not be changed while A/D conversion is in progress.
Relationships Between fsys Frequencies and A/D Conversion Times
accuracy occurs unless the conversion time is set to 8.6 µs or more.
32 MHz
20 MHz
16 MHz
10 MHz
8 MHz
fsys
15
23












7
7
14
22












6
6
TMP1941AF-16
Wake-up
sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
Wake-up
sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
Wake-up INT2 sensitivity
00: Low level
01: High level
10: Falling edge
11: Rising edge
EMCG01
EMCG11
EMCG21
13
21



Don’t use.
5
5
1
1
1
10.75 µs
fsys/2
17.2 µs
21.5 µs
8.6 µs
R/W
R/W
R/W
EMCG00
EMCG10
EMCG20
12
20



4
4
0
0
0
INT0
INT1
Conversion Clock
10.75 µs
17.2 µs
21.5 µs
34.4 µs
43.0 µs
fsys/4
11
19












3
3
10
18












2
2
TMP1941AF
ADC conversion clock
(fadc) select
ADCCK1
00: fsys/2
01: fsys/4
10: fsys/8
11: Don’t use.
fsys/8
21.5 µs
34.4 µs
43.0 µs
68.8 µs
86.0 µs
R/W
17









1
1
9
0
2003-03-27
INT0
enable
0: Disable
1: Enable
INT1
enable
0: Disable
1: Enable
INT2
enable
0: Disable
1: Enable
ADCCK0
INT0EN
INT1EN
INT2EN
R/W
R/W
R/W
R/W
16
0
0
8
0
0
0
0