tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 48

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Note 1: When a DSU ICE is used, P37 and A0-A7 function as debug interface signals.
Note 2: P37 and P87 should be held at the prescribed logic states for one system clock cycle before and after the rising
NMI
PLLOFF
RESET
PA6
SO
SDA
PA7
SI
SCL
ALE
AM1
AM0
TEST
VREFH
VREFL
AVCC
AVSS
X1/X2
DVCC,
CVCC
DVSS,
CVSS
Pin Name
DSU Debug Interface
If the DSU pin is sampled low at the rising edge of RESET , the Port A pins are configured as interface signals for an
external real-time debug system. The DSU pin has an internal pullup resistor.
(PA7)
DCLK
(PA0)
(PA5)
PCST[2]
(PA1)
PCST[1]
(PA2)
PCST[0]
(PA3)
SDI/ DINT
(PA6)
SDAO/TPC
(PA4)
DRESET
DBGE
The following shows the DSU interface signals.
edge of RESET , with the RESET signal being stable in either logic state.
# of Pins
1
1
1
1
1
1
1
1
1
1
1
1
1
2
5
5
O
O
O
O
O
I
I
I
Input/output
Output
Input/output
Input/output
Input
Input/output
Output
Input
Input
Input
Input
Input
Input
Input
Input


Input/output


Type
Debug Reset
Debug Clock
DCLK signal for an external real-time debug system
Debugger Enable
PC Trace Status [2]
PCTS[2] signal for an external real-time debug system
PC Trace Status [1]
PCST[1] signal for an external real-time debug system
PC Trace Status [0]
PCTS[0] signal for an external real-time debug system
Serial Data Input / Debug Interrupt
SDI/ DINT signal for an external real-time debug system
Serial Data and Address Output / Target PC
SDAO/TPC signal for an external real-time debug system
DRESET signal for an external real-time debug system
DBGE signal for an external real-time debug system
Figure 2.2 DSU Interface Signals
Port A6: Programmable as input or output
Data transmit pin when the Serial Bus Interface is in SIO mode
Data transmit/receive pin when the Serial Bus Interface is in I
as a push-pull or open-drain output
Port A7: Programmable as input or output
Data receive pin when the Serial Bus Interface is in SIO mode
Clock input/output pin when the Serial Bus Interface is in I
programmable as a push-pull or open-drain output
Address Latch Enable (This signal is driven out only when external memory is
accessed.)
Nonmaskable Interrupt Request: Causes an NMI interrupt on the falling edge
AM1 should be tied to logic 0.
AM0 should be tied to logic 0 when configuring a 16-bit or mixed 8-/16-bit bus.
AM0 should be tied to logic 1 when configuring a 8-bit bus.
Test pin: This pin should be left open or tied to ground.
This pin should be tied to logic 1 when the frequency multiplied clock from the PLL is
used; otherwise, it should be tied to logic 0.
Reset (with internal pull-up resister): Initializes the whole TMP1941AF.
Input pin for high reference voltage for the A/D Converter. This pin should be
connected to the AVCC pin when the A/D Converter is not used.
Input pin for low reference voltage for the A/D Converter. This pin should be connected
to the AVSS pin when the A/D Converter is not used.
Power supply pin for the A/D Converter. This pin should always be connected to power
supply even when the A/D Converter is not used.
Ground pin for the A/D Converter. This pin should always be connected to ground
even when the A/D Converter is not used.
Connection pins for a high-speed crystal
Power supply pins
Ground pins (0 V)
TMP1941AF-8
Function
TMP1941AF
2
C mode; as an output,
2
C mode; programmable
2003-03-27