tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 111

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.2.3
ALE (ALESEL = 0)
AD[15:0]
ALE (ALESEL = 1)
AD[15:0]
ALE Pulse Width
SYSCR3 register within the CG. The default is 1.5 cycles. This setting applies to the whole external
address space.
The ALE pulse width is programmed to 0.5 or 1.5 clock cycles through the ALESEL bit of the
Figure 8.8 shows read cycle timing, with the ALE width programmed to 0.5 and 1.5 clock cycles.
A[23:16]
AD[15:0]
ALE
RD
Figure 8.8 Read Cycle Timing (ALE = 0.5 and 1.5 Clock Cycles)
ALE = 0. 5 Clock Cycles
tsys
ADR
Upper Address
Figure 8.7 ALE Pulse Width
DATA
TMP1941AF-71
tsys
0.5 Clock Cycles
ADR
ALE = 1. 5 Clock Cycles
Upper Address
1.5 Clock Cycles
DATA
TMP1941AF
2003-03-27