tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 51

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

5.
(Selectable peripheral operation)
Note 1: Before a transition to SLOW or SLEEP mode can occur, the low-speed oscillator (fs) must be oscillating
Note 2: After SLEEP mode is exited, the TMP1941AF returns to the mode it was in before entering SLEEP mode.
Note 3: After STOP mode is exited, the TMP1941AF returns to the mode specified by the System Control Register 0
Clock/Standby Control
supplied from the X1/X2 pins, and Dual-Clock mode which operates off of the high-speed clock supplied from
the X1/X2 pins and the low-speed clock supplied from the XT1/XT2 pins.
(Selectable peripheral operation)
The TMP1941AF has two clocking modes: Single-Clock mode which operates off of the high-speed clock
Figure 5.1 shows the transitions between clocking modes in Single-Clock mode and Dual-Clock mode.
(CPU halted)
IDLE Mode
(Only RTC is active.)
stably.
(SYSCR0). See Section 5.2.
(CPU halted)
IDLE Mode
SLEEP Mode
(fs only)
A. When the PLL clock is used
fosc:
fs:
fpll:
fc:
fgear:
fsys:
fperiph:
fc = fpll = fosc × 4
NORMAL Mode
∴fsys = fosc / 2
Figure 5.2 Default Clock Frequencies in NORMAL Mode
fperiph = fsys
fsys = fc / 8
Reset
Clock frequency supplied via the X1 and X2 pins
Clock frequency supplied via the XT1 and XT2 pins
PLL multiplied clock frequency (x4)
Clock frequency selected by the PLLOFF pin
Clock frequency selected by the GEAR[1:0] bits in the SYSCR1
System clock frequency selected by the SYSCK bit in the SYSCR1
Clock source for the prescalers inside on-chip peripherals
Instruction
Figure 5.1 Standby Modes Flow Diagram
Reset released
PLLOFF = 1
PLL used
Instruction
Instruction
Interrupt
Interrupt
Instruction
Interrupt
Interrupt
(a) Single-Clock Mode
(b) Dual-Clock Mode
TMP1941AF-11
NORMAL Mode
(fc/gear_value)
SLOW Mode
(fc / gear_value)
NORMAL Mode
Reset
(fs)
Reset
B. When the PLL is not used
Reset released
Reset released
∴fsys = fosc / 16
NORMAL Mode
fperiph = fsys
Interrupt
fc = fosc / 2
fsys = fc / 8
Reset
Instruction
Interrupt
Instruction
Interrupt
Reset released
PLLOFF = 0
PLL not used
Instruction
TMP1941AF
(Whole chip halted)
(Whole chip halted)
STOP Mode
STOP Mode
2003-03-27