tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 46

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

2.2
RD
HWR
BUSRQ
BUSAK
R
DSU
CS
CS
CS2
CS3
AD0–AD7
AD8–AD15
A8–A15
A0–A7
A16–A23
WR
WAIT
P37
P40
P41
P42
P43
P44
SCOUT
P50–P57
AN0–AN7
ADTRG
P70
TA0IN
TXD3
P71
TA1OUT
RXD3
P72
TA2IN
TXD4
P73
TA3OUT
RXD4
P74
TB0IN0
INT5
Pin Name
/
0
1
W
Pin Usage Information
for multi-function pins.
Table 2.1 lists the input and output pins of the TMP1941AF, including alternate pin names and functions
# of Pins
8
8
8
1
1
1
1
1
1
1
1
1
1
1
1
1
8
1
1
1
1
1
Input/output
Input/output
Output
Output
Output
Output
Output
Output
Input
Input
Output
Output
Input/output
Input
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input/output
Output
Input
Input
Input
Input/output
Input
Output
Input/output
Output
Input
Input/output
Input
Output
Input/output
Output
Input
Input/output
Input
Input
Type
Table 2.1 Pin Names and Functions
Address (Lower): Bits 0-7 of the address/data bus
Address/Data (Upper): Bits 8-15 of the address/data bus
Address: Bits 8-15 of the address bus
Address: Bits 0-7 of the address bus
Address: Bits 16-23 of the address bus
Read Strobe: Asserted during a read operation from an external memory device
Write Strobe: Asserted during a write operation on D0-D7
Higher Write Strobe: Asserted during a write operation on D8-D15
Wait: Causes the CPU to suspend external bus activity
Bus Request: Asserted by an external bus master to request bus mastership
Bus Acknowledge: Indicates that the CPU has relinquished the bus in response to
Read/Write: Indicates the direction of data transfer on the bus: 1 = read or dummy
cycle, 0 = write cycle
Port 37: Programmable as input or output (with internal pull-up resister)
DSU Enable: If this pin is sampled low at the rising edge of RESET , the TMP1941AF
enters DSU mode for software debugging using an external real-time debug system. If
this pin is sampled as high at the rising edge of RESET , the TMP1941AF enters
NORMAL mode.
Port 40: Programmable as input or output (with internal pull-up resister)
Chip Select 0: Asserted low to enable external devices at programmed addresses
Port 41: Programmable as input or output (with internal pull-up resister)
Chip Select 1: Asserted low to enable external devices at programmed addresses
Port 42: Programmable as input or output (with internal pull-up resister)
Chip Select 2: Asserted low to enable external devices at programmed addresses
Port 43: Programmable as input or output (with internal pull-up resister)
Chip Select 3: Asserted low to enable external devices at programmed addresses
Port 44: Programmable as input or output
System Clock Output: Drives out a clock signal at the same frequency as the CPU
clock (high-speed or low-speed)
Port 5: Input-only
Analog Input: Input to the on-chip A/D Converter
A/D Trigger: Starts an A/D conversion (multiplexed with P53)
Port 70: Programmable as input or output
8-Bit Timer 0 Input: Input to Timer 0
Serial Transmit Data 3: Programmable as a push-pull or open-drain output
Port 71: Programmable as input or output
8-Bit Timer 1 Output: Output from either Timer 0 or Timer 1
Serial Receive Data 3
Port 72: Programmable as input or output
8-Bit Timer 2 Input: Input to Timer 2
Serial Transmit Data 4: Programmable as a push-pull or open-drain output
Port 73: Programmable as input or output
8-Bit Timer 3 Output: Output from either Timer 2 or Timer 3
Serial Receive Data 4
Port 74: Programmable as input or output
16-Bit Timer 0 Input 0: Count/capture trigger input to 16-bit Timer 0
Interrupt Request 5: Programmable to be high-level, low-level, rising-edge or falling-
edge sensitive
BUSRQ
TMP1941AF-6
.
Function
TMP1941AF
2003-03-27