tmp1941af TOSHIBA Semiconductor CORPORATION, tmp1941af Datasheet - Page 113

• Manufacturer Part Number: tmp1941af
• Description: 32-bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

8.3
8.3.1
8.3.2
Bus Arbitration
arbitration control signals, BUSRQ and BUSAK , are used to determine the bus master. One or more of the
external devices on the bus can have the capability of becoming bus master for the external bus, but not the
TMP1941AF internal bus.
The TMP1941AF provides support for an external bus master to take control of the external bus. Two bus
Bus Access Control
Bus). Thus, external bus masters cannot access the TMP1941AF’s on-chip memory and peripherals.
The External Bus Interface (EBIF) logic in the TMP1941AF manages the arbitration of the external
bus; the CPU and on-chip DMAC do not participate in any way in this bus arbitration. During external
bus mastership, the CPU and the on-chip DMAC can access the internal memory (RAM and ROM) and
registers.
regain the bus until the external bus master releases the bus. If the CPU or the on-chip DMAC issues an
external memory access request, it is forced to wait until the TMP1941AF regains the bus. Therefore,
should BUSRQ be left asserted for a long time, the TMP1941AF might suffer system lockups.
Bus Arbitration Flow
TMP1941AF samples BUSRQ at the end of each external bus cycle, as seen on its internal bus (G-
Bus). When the TMP1941AF has made an internal decision to grant the bus, it asserts BUSAK to
indicate to the requesting device that the bus is available. At the same time, the TMP1941AF puts the
address bus, the data bus and bus control signals in the high-impedance state.
(dynamic bus sizing). In that case, the TMP1941AF does not grant the bus until the entire transfer is
complete.
cycles to allow for sufficient read recovery time. In dummy cycles, the TMP1941AF has already
internally initiated a bus cycle on the G-Bus for the next external access. The TMP1941AF can only
accept an external bus request at the boundary of an internal G-Bus bus cycle. Therefore, if BUSRQ is
asserted during a dummy cycle, the TMP1941AF grants the bus after it completes the next external bus
cycle.
External bus masters can gain control of the external bus, but not the TMP1941AF internal bus (G-
Once an external device assumes bus mastership, the CPU or the on-chip DMAC has no way to
External devices capable of becoming bus masters assert BUSRQ to request the bus. The
A load or store may require multiple bus cycles, depending on the port size of the addressed device
The TMP1941AF, if so programmed, automatically inserts dummy cycles between back-to-back bus
An external bus master must keep BUSRQ asserted until it is granted the bus.
A timing diagram of the bus arbitration sequence is shown in Figure 8.11.
TMP1941AF-73
TMP1941AF
2003-03-27