r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1012
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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20. Graphics Data Translation Accelerator (GDTA)
20.3.4
GACICR is in the GDTA common register block and clears interrupt source indication for each
module. Bits in this register are read as 0.
Rev.1.00 Jan. 10, 2008 Page 982 of 1658
REJ09B0261-0100
Initial value:
Initial value:
Bit
31 to 4
3
2
1
0
R/W:
R/W:
BIt:
BIt:
GA Interrupt Source Indication Clear Register (GACICR)
Bit Name
⎯
MC_ERCR
CL_ERCR
MC_ENCR
CL_ENCR
31
15
⎯
⎯
⎯
⎯
0
0
30
⎯
⎯
14
⎯
⎯
0
0
29
⎯
⎯
13
⎯
⎯
0
0
Initial
Value
All 0
0
0
0
0
28
12
⎯
⎯
⎯
⎯
0
0
R/W
⎯
W
W
W
W
27
11
⎯
⎯
⎯
⎯
0
0
26
10
⎯
⎯
⎯
⎯
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Clears indication of an MC error interrupt (clears the
MC_ERR bit)
0: No effect
1: Clears error interrupt indication
Clears indication of a CL error interrupt (clears the
CL_ERR bit)
0: No effect
1: Clears error interrupt indication
Clears indication of an MC processing end interrupt
(clears the MC_END bit)
0: No effect
1: Clears processing end interrupt indication
Clears indication of a CL processing end interrupt (clears
the CL_END bit)
0: No effect
1: Clears processing end interrupt indication
25
⎯
⎯
⎯
⎯
0
9
0
24
⎯
⎯
⎯
⎯
0
8
0
23
⎯
⎯
⎯
⎯
0
7
0
22
⎯
⎯
⎯
⎯
0
6
0
21
⎯
⎯
⎯
⎯
0
5
0
20
⎯
⎯
⎯
⎯
0
4
0
ERCR
MC_
19
⎯
⎯
W
0
3
0
ERCR
CL_
18
⎯
⎯
W
0
2
0
ENCR
MC_
17
⎯
⎯
W
0
1
0
ENCR
CL_
16
⎯
⎯
W
0
0
0
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