r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 529

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

12.4.8
The SDRAM refresh control register 0 (DBRFCNT0) is a readable/writable register. It is
initialized only upon power-on reset.
Initial value:
Initial value:
Bit
31 to 17 ⎯
16
15 to 1
R/W:
R/W:
BIt:
BIt:
SDRAM Refresh Control Register 0 (DBRFCNT0)
Bit Name
ARFEN
⎯
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
13
⎯
⎯
Initial
Value
All 0
0
All 0
R
R
0
0
28
⎯
12
⎯
R
R
0
0
27
⎯
11
⎯
R
R
0
0
R/W
R
R/W
R
26
10
⎯
⎯
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
Auto-Refresh Enable Bit
Enables or disables automatic issue of auto-refresh.
The auto-refresh command is issued periodically
according to the settings of DBRFCNT1/2.
For details on the auto-refresh command issue timing,
refer to section 12.5.5, Auto-Refresh Operation.
0: Disables automatic issue of auto-refresh.
1: Enables automatic issue of auto-refresh.
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
25
⎯
⎯
R
R
0
9
0
24
⎯
⎯
R
R
0
8
0
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 499 of 1658
22
⎯
⎯
R
R
0
6
0
12. DDR2-SDRAM Interface (DBSC2)
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
ARFEN
SRFEN
R/W
R/W
16
0
0
0