r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 711

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

14.3.7
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit
31
30
29, 28
Initial value:
Initial value:
R/W:
R/W:
Note: * R/(W): To clear the flag, 0 can be written to.
Bit:
Bit:
DMA Channel Control Registers 0 to 11 (CHCR0 to CHCR11)
Bit Name
⎯
LCKN
⎯
R/W
31
15
R
0
0
DM[1:0]
LCKN
R/W
R/W
30
14
1
0
R/W
29
13
Initial
Value
0
1
All 0
R
0
0
SM[1:0]
R/W
28
12
R
0
0
R/W
R/W
27
11
R/W
R
R/W
R
0
0
RPT[2:0]
R/W
R/W
26
10
0
0
RS[3:0]
Descriptions
Reserved
This bit is always read as 0. The write value should
always be 0.
Bus Lock Signal Disable
Specifies whether the bus lock signal output is enabled
or disabled during a read instruction for the
SuperHyway bus. This bit is valid in cycle steal mode.
Clear this bit to 0 in burst mode.
If the bus lock signal is disabled, the bus request from
the bus master other than the DMAC can be accepted.
This can improve the bus usage efficiency in the
system.
For channels 0 to 5, this bit can be set to 0 or 1.
For channels 6 to 11, do not clear this bit to 0. The write
value should always be 1.
0: Bus lock signal output enabled
1: Bus lock signal output disabled
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W
R/W
25
0
9
0
R/W
24
R
0
8
0
R/W
R/W
DO
23
DL
0
0
7
14. Direct Memory Access Controller (DMAC)
R/W
Rev.1.00 Jan. 10, 2008 Page 681 of 1658
R/W
DS
RL
22
6
0
0
R/W
TB
21
R
0
5
0
R/W R/(W)* R/W
R/W
TS2
20
0
4
0
TS[1:0]
R/W
HE
19
0
3
0
REJ09B0261-0100
R/W R/(W)*
HIE
18
IE
0
2
0
R/W
AM
17
TE
0
1
0
R/W
R/W
DE
16
AL
0
0
0