r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 513
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Part Number:
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12.4.2
The SDRAM operation enable register (DBEN) is a readable/writable register. It is initialized only
upon power-on reset.
Initial value:
Initial value:
Bit
31 to 1
0
R/W:
R/W:
BIt:
BIt:
SDRAM Operation Enable Register (DBEN)
Bit Name
⎯
ACEN
31
15
⎯
⎯
R
R
0
0
30
14
⎯
⎯
R
R
0
0
29
13
⎯
⎯
R
R
0
0
Initial
Value
All 0
0
28
⎯
12
⎯
R
R
0
0
27
⎯
11
⎯
R
R
0
0
R/W
R
R/W
26
10
⎯
⎯
R
R
0
0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Operation when a value other than 0 is written is not
guaranteed.
SDRAM Access Enable Bit
By setting this bit, data accessing of SDRAM is enabled.
When set to 0, access is disabled; when set to 1,
access is enabled. When access is disabled, attempts
to access SDRAM are ignored. This bit is used for the
initialization sequence or self-refresh operation.
0: Disables access
1: Enables access
25
⎯
⎯
R
R
0
9
0
24
⎯
⎯
R
R
0
8
0
23
⎯
⎯
R
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 483 of 1658
22
⎯
⎯
R
R
0
6
0
12. DDR2-SDRAM Interface (DBSC2)
21
⎯
⎯
R
R
0
5
0
20
⎯
⎯
R
R
0
4
0
19
⎯
⎯
R
R
0
3
0
REJ09B0261-0100
18
⎯
⎯
R
R
0
2
0
17
⎯
⎯
R
R
0
1
0
ACEN
R/W
16
⎯
R
0
0
0
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