r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 989

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

19.5.2
When in master mode, a CSYNC (composite sync) signal is output. EQWR is used to set the low-
level pulse width of the CSYNC equal pulse. SPWR is used to set the low-level pulse width of the
CSYNC separation pulse.
The CSYNC waveform is selected using the CSY bit in DSMR.
Figure 19.14 CSYNC Timing Chart (Non-Interlaced Mode, First Half of Interlace Frame)
(CSY = 00)
(CSY = 10)
(CSY = 11)
HSYNC
VSYNC
CSYNC
HSW
CSYNC
1/2HC
When HC is odd, it is rounded to an even value.
Equivalent pulse:
3 rasters
HC
EQW
Equivalent pulse:
2.5 rasters
SPW
Separation pulse:
2.5 rasters
Separation pulse:
3 rasters
Equivalent pulse:
2.5 rasters
Equivalent pulse:
3 rasters
Rev.1.00 Jan. 10, 2008 Page 959 of 1658
19. Display Unit (DU)
REJ09B0261-0100