r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 268
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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8. Caches
8.7
This LSI supports two 32-byte store queues (SQs) to perform high-speed writes to external
memory.
8.7.1
There are two 32-byte store queues, SQ0 and SQ1, as shown in figure 8.9. These two store queues
can be set independently.
8.7.2
A write to the SQs can be performed using a store instruction for addresses H'E000 0000 to
H'E3FF FFFC in the P4 area. A longword or quadword access size can be used. The meanings of
the address bits are as follows:
Rev.1.00 Jan. 10, 2008 Page 238 of 1658
REJ09B0261-0100
[31:26]
[25:6]
[5]
[4:2]
[1:0]
Store Queues
SQ Configuration
Writing to SQ
: 111000
: Don't care
: 0/1
: LW specification
: 00
SQ0
SQ1
SQ0[0]
SQ1[0]
4 byte
Figure 8.9 Store Queue Configuration
SQ0[1]
SQ1[1]
4 byte
Store queue specification
Used for external memory transfer/access right
0: SQ0 specification
1: SQ1 specification
Specifies longword position in SQ0/SQ1
Fixed at 0
SQ0[2]
SQ1[2]
4 byte
SQ0[3]
SQ1[3]
4 byte
SQ0[4]
SQ1[4]
4 byte
SQ0[5]
SQ1[5]
4 byte
SQ0[6]
SQ1[6]
4 byte
SQ0[7]
SQ1[7]
4 byte
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