r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 748

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

14. Direct Memory Access Controller (DMAC)
Rev.1.00 Jan. 10, 2008 Page 718 of 1658
REJ09B0261-0100
Notes: 1. In repeat mode, a transfer request is acceptted with TE =1 when HIE = 1 and HE = 0
TCR – 1 → TCR, SAR, and DAR updated
Reload mode: TCRBL – 1 → TCRBL
SAR, DAR, TCR, CHCR, DMAOR
2. In auto-request mode, transfer starts when bits NMIF, AE, and TE are all 0 or bits TE
3. DREQ is level detection (external request) in burst mode or cycle-steral mode.
4. DREQ is edge detection (external request) or auto request in burst mode.
5. Loading to SAR and DAR differs according to the operating conditions in each mode.
6. TCRBH and TCRBL refer to TCRB23 to TCRB16 and TCRB7 to TCRB0 respectively.
SARB, DARB, TCRB, DMARS
Transfer (1 transfer unit);
(half end interrupt is enable and clear the HE to 0 after HE is set to 1).
and HIE are 1 and HE is 0 (in repeat mode), and bits DE and DME are set to 1.
DMINT interrupt request
Transfer request occurs?
NMIF = 1 or AE =1 or
DE = 0 or DME = 0?
TE, AE, NMIF = 0?
DE, DME = 1 and
Reload mode?
Repeat mode?
Initial settings
Normal end
Yes
Yes
Yes
No
TCR = 0?
(IE = 1)
No
No
TE = 1
Start
Figure 14.11 Flowchart of DMA Transfer
*
*
1
2
Yes
Yes
Yes
No
No
No
No
*
6
TCRB → TCR load
TCRBH → TCRBL load
HIE = 0 or HE = 1?
SARB/DARB load
SARB/DARB load
Yes
TCRBL = 0?
Yes
No
*
No
5
*
*
5
6
HE = 1, DMINT interrupt
NMIF = 1 or AE = 1 or
DE = 0 or DME = 0?
TCR = TCRB/2?
request (HIE = 1)
Transfer end
Yes
Yes
*
4
transfer request mode
Bus mode, DREQ
detection system,
No
*
3