r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 1121

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

In serial reception, the SCIF operates as follows.
1. The SCIF is initialized internally in synchronization with the input or output of the
2. The receive data is stored in SCRSR in LSB-to-MSB order.
3. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
Figure 21.20 shows an example of the SCIF reception operation.
synchronization clock.
After receiving the data, the SCIF checks whether the receive data can be transferred from
SCRSR to SCFRDR. If this check is passed, the receive data is stored in SCFRDR. If an
overrun error is detected in the error check, reception cannot continue.
interrupt (RXI) request is generated.
If the RIE bit in SCSCR is set to 1 when the ORER flag changes to 1, a break interrupt (BRI)
request is generated.
Figure 21.19 Sample Serial Reception Flowchart (2)
No
Clear ORER flag in SCLSR to 0
Overrun error handling
Error handling
ORER = 1?
21. Serial Communication Interface with FIFO (SCIF)
End
Yes
Rev.1.00 Jan. 10, 2008 Page 1091 of 1658
REJ09B0261-0100