r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 793
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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16.3.1
WDTST is a 32-bit readable/writable register that specifies the time until watchdog timer counter
WDTCNT overflows. The time until WDTCNT overflows becomes minimum when H'5A00 0001
is set, and maximum when H'5A00 0000 is set.
WDTST should be written as a longword unit, with H'5A in the most significant byte. The value
read from this byte is always H'00. WDTST is only rest by a power-on reset caused by the
PRESET pin.
Initial value:
Initial value:
Bit
31 to 24
23 to 12
11 to 0
R/W:
R/W:
Bit:
Bit:
Watchdog Timer Stop Time Register (WDTST)
Bit Name
(Code for
writing)
⎯
WDTST
R/W
31
15
⎯
R
0
0
R/W
30
14
⎯
R
0
0
R/W
29
13
⎯
Code for writing (H'5A)
R
0
0
Initial
Value
All 0
All 0
All 0
R/W
28
12
⎯
R
0
0
R/W
R/W
R/W
R/W
R
R/W
27
11
0
0
R/W
R/W
26
10
0
0
Description
Code for writing (H'5A)
These bits are always read as H'00. When writing to
this register, the value written to these bits must be
H'5A.
Reserved
These bits are always read as 0. The write value
should always be 0.
Timer Stop
These bits set the counter value at which WDTCNT
overflows.
H'001: Minimum overflow value
H'000: Maximum overflow value
R/W
R/W
25
0
9
0
R/W
R/W
24
0
8
0
R/W
23
⎯
R
0
7
0
Rev.1.00 Jan. 10, 2008 Page 763 of 1658
R/W
22
⎯
R
0
6
0
WDTST
16. Watchdog Timer and Reset (WDT)
R/W
21
⎯
R
0
5
0
R/W
20
⎯
R
0
4
0
R/W
19
⎯
R
0
3
0
REJ09B0261-0100
R/W
18
⎯
R
0
2
0
R/W
17
⎯
R
0
1
0
R/W
16
⎯
R
0
0
0
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