r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 567
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Part Number:
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command, the constraint tRCD between the ACT command and READ command, and the
constraint tRAS between the ACT command and the PRE command are involved. The DBSC2
waits to issue commands until each of the constraints is satisfied.
MCK0,
MCK1
MCKE
MCS
MRAS
MCAS
MWE
MA[14:11]
MA[9:0]
MA[10]
MBA[2:0]
MDQS[3:0]
MDM[3:0]
MDQ[31:0]
SDRAM
command
bank A
PRE
Valid
Invalid
tRP
= 3 cycles
Invalid
Invalid
Figure 12.14 tRP, tRCD, CL, and tRAS
High level
bank A
ACT
Valid
Valid
Valid
Invalid
Invalid
Invalid
Invalid
tRAS
= 9 cycles
= 3 cycles
tRCD
READ
bank A
Invalid
Valid
Valid
Valid
CL
= 3 cycles
Rev.1.00 Jan. 10, 2008 Page 537 of 1658
12. DDR2-SDRAM Interface (DBSC2)
Invalid
Invalid
Read data
Invalid
bank A
REJ09B0261-0100
PRE
Valid
Invalid
Invalid
Invalid
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