r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 386

• Manufacturer Part Number: r8a77850anbg
• Description: Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
• Manufacturer: Renesas Electronics Corporation.

11. Local Bus State Controller (LBSC)
Notes: 1. The memory bus width is specified by the external pins.
Rev.1.00 Jan. 10, 2008 Page 356 of 1658
REJ09B0261-0100
Area
6
7*
Area 0:
Area 1:
Area 2:
Area 3:
Area 4:
Area 5: (1st half) H'1400 0000
Area 6: (1st half) H'1800 0000
Note: * Any of these memory devices can be connected to each of the 1st and 2nd halves of the area.
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(2nd half) H'1A00 0000
(2nd half) H'1600 0000
2. The memory bus width is specified by the register.
3. These areas can be allocated to DDR2-SDRAM by setting MMSELR. For details, see
4. This area can be allocated to PCI memory by setting MMSELR. For details, see section
5. When the PCMCIA interface is used, the bus width should be 8 or 16 bits.
6. Do not access the reserved area. If the reserved area is accessed, correct operation is
7. If the LBSC is requested to perform 8- or 16-byte access by the bus master, the LBSC
External
addresses
H'1800 0000 to
H'1BFF FFFF
H'1C00 0000 to
H'1FFF FFFF
section 12, DDR2-SDRAM Interface (DBSC2).
13, PCI Controller (PCIC).
not be guaranteed.
performs accesses two or four times respectively with 32-bit access size.
H'0C00 0000
H'0000 0000
H'0400 0000
H'0800 0000
H'1000 0000
Figure 11.3 Local Bus Memory Space Allocation
Size
64 Mbytes
64 Mbytes ⎯
SRAM/Burst ROM/MPX
(DDR2-SDRAM)
SRAM/Burst ROM/MPX
SRAM/Burst ROM/MPX/Byte control SRAM
SRAM/Burst ROM/MPX
(DDR2-SDRAM)
SRAM/Burst ROM/MPX/ Byte control SRAM
(DDR2-SDRAM/PCI)
SRAM/Burst ROM/MPX/PCMCIA *
(DDR2-SDRAM)
SRAM/Burst ROM/MPX/PCMCIA *
Connectable
Memory
SRAM
MPX
Burst ROM
PCMCIA
Specifiable Bus
Width (bits)
8, 16, 32, 64*
32, 64*
8, 16, 32, 64*
8, 16*
⎯
2, 5
2
2
2
The PCMCIA interface is
also used for memory I/O
cards.
Access Size*
8/16/32 bits,
32 bytes
—
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