r8a77850anbg Renesas Electronics Corporation., r8a77850anbg Datasheet - Page 531
r8a77850anbg
Manufacturer Part Number
r8a77850anbg
Description
Renesas 32-bit Risc Microcomputer Superh? Risc Engine Family
Manufacturer
Renesas Electronics Corporation.
Datasheet
1.R8A77850ANBG.pdf
(1692 pages)
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Note: Writing to this register should be performed only when the following condition is met.
Bit
12 to 0
•
Bit Name
TREFI12 to
TREFI0
When automatic issue of auto-refresh is disabled (when the ARFEN bit in the
DBRFCNT0 register is cleared to 0.).
Initial
Value
0 0010
0000 0000
R/W
R/W
Description
Average Refresh Interval Setting Bits
These bits set the average interval for auto-refresh
operation. Upon refresh execution, this value is added
to the refresh interval count register.
The number of cycles is the number of DDR clock
cycles.
0 0000 0000 0000: Setting prohibited (If specified,
0 0000 0011 1111: Setting prohibited (If specified,
0 0000 0100 0000: 65 cycles
0 0000 0100 0001: 66 cycles
1 1111 1111 1111: 8192 cycles
:
:
Rev.1.00 Jan. 10, 2008 Page 501 of 1658
correct operation cannot be
guaranteed.)
correct operation cannot be
guaranteed.)
12. DDR2-SDRAM Interface (DBSC2)
REJ09B0261-0100
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